Clock signals are periodic digital signals (e.g., rectangular form) which are used in a variety of digital circuits, for example to coordinate the function of circuit components. For example, a clock signal oscillates between a first logical state (e.g., logical "1" at a "high" voltage level) and second logical state (e.g., logical "0" at ground level) with a predetermined ratio between logical "1" and "0" times.
Some components locally use private clock signals which are sometimes combined into further clock signals. Overlapping of clock signals (e.g., two signals simultaneously at "1") is usually not desirable. When generating and distributing clock signals, propagation delays and changes of the signal form should be limited. Delays occur, for example, in logic gates (e.g., inverters, and-, or-gates, etc.) and/or in connection lines (within or outside the circuit). Signal form changes occur, for example, due to parasitic capacities and inductivities. Further, these and other unwanted effects depend on the manufacturing process.
In order to maintain features such as reliability, high operation speed, accuracy, etc., non-overlap clock generators may require, among other things, (a) the appropriate circuit layout which is expensive to provide, (b) calibration during manufacturing adding further costs, and (c) feedback loops with introduce further delay and which shorten the duty time (i.e. on-time) of the output clock. This is especially important for clock signals at high frequencies such as in the GHz-range.
Examples for clock drivers can be found, of example, in reference [1] U.S. Pat. 5,444,405 to Troung et al. and [2] U.S. Pat. No. 5,453,707 to Hiratsuka et al.
The present invention seeks to provide clock generators which mitigate or avoid these and other disadvantages and limitations of the prior art.